1. Field of the Invention
The present invention relates to a serial/parallel converter that enables fast processing with low current consumption.
2. Related Arts
A serial/parallel converter is frequently employed in an integrated semiconductor circuit. Such a serial/parallel converter is, for example, one by which a plurality of serially input address signals from a system are output in parallel internally. This converter is employed for a system having an extremely high transfer rate, such as 800 Mbps or 1.6 Gbps, and a plurality of address signals are transmitted at an extremely high transfer rate. It is, therefore, necessary for the internal serial/parallel converter to latch, in a short period of time, address signals which are input at high speed and to output them in parallel with the same phase.
FIG. 35 is a diagram illustrating a conventional serial/parallel converter. FIG. 36 is a timing chart for the serial/parallel converter in FIG. 35. In this circuit, a clock CLK is amplified by a clock amplifier C36 and an internal clock S55 is generated. The internal clock S55 is divided by 4 by a frequency divider C45, and a clock S64 for final latching is generated. Input data DATA is amplified by a data amplifier C37, and is transferred to corresponding flip-flop circuits C38 through C44 at the leading edges or trailing edges of the internal clock S55. That is, the flip-flop circuits C38, C39, C40 and C41 latch the input data DATA at the leading edges of the internal clock S55, while the flip-flops C42, C43 and C44 latch the input data DATA at the trailing edges of the internal clock S55.
As is shown in FIG. 36, the data DATA is transmitted synchronously with the leading edges of the clock CLK (internal clock S55), and is synchronously latched by the flip-flops with the leading edges and the trailing edges of the internal clock S55. In this example circuit, at time T1, where data Dn, Dn+1, Dn+2 and Dn+3 are latched by the corresponding flip-flops C38, C39, C40 and C41, these data are latched by the flip-flops C46, C47, C48 and C49 at the leading edge of a final latch clock S64. During a period equivalent to four times the cycle of the clock CLK, the flip-flops C46 through C49 latch the data and output in parallel a set of four data (S65.about.S68)to four output terminals S65 through S68.
As is described above, the conventional serial/parallel converter converts four serial data sets into four parallel data sets in synchronization with the leading edge of the 1/4 frequency divided clock S64.
The above serial/parallel converter requires eleven flip-flop circuits for 4-bit serial/parallel conversion. In addition, since the flip-flops C38 through C44 perform data latching four times and the flip-flops C46 through C49 perform data latching one time, a total of 32 operations by the flip-flops are required for one conversion process, and the current consumption is increased. According to this, for the conversion of 8-bit serial data, the number of required flip-flop circuits and the number of operations will be increased and the current consumption will be also increased.
Further, when the frequency of the input clock is increased, the operation speed of the flip-flop that performs synchronous latching with the input clock has to correspond to that speed. Thus, the circuit must be so designed that it can be operated at a high speed with a higher current consumption. Therefore, when a large number of flip-flops are operated for one serial/parallel conversion, the current consumption will be further increased. In addition, for faster processing, a serial/parallel converter is required that can cope with the input of data synchronized with the leading edge and the trailing edge of the input clock.
The serial input data is supplied in synchronous with a flag signal indicating the head of the serial data, therefore it is required that a fetching of the serial input data should be initiated using the flag signal as a trigger, and a parallel data output should be output at a certain timing signal. However, it is not easy to generate the timing signal for parallel data output after the last serial data has been fetched. Especially difficult, while taking into account an operating delay time for a flip-flop circuit for fetching the last serial data, is generating a timing signal for parallel data output at the shortest timing.
In addition, a circuit is required which generates a control clock for fetching serial data using an externally supplied flag signal as a trigger. Since this circuit has its own operating delay time, the input of serial data synchronized with a fast clock is affected accordingly. Therefore, a circuit is required which can fetch serial data without being affected by the timing of a flag signal.